This invention relates generally to an integrated memory device and, more specifically, to a method and apparatus for the page recall of data in an NVDRAM memory device.
An NVDRAM cell has been described in "A New Architecture for the NVRAM--An EEPROM Backed-Up Dynamic RAM", IEEE Journal of Solid State Circuits, Vol. 23, No. 1, Feb. 1988; by Chuang et al. in U.S. Pat. No. 4,611,309; and in Yamauchi et al., "A Versatile Stacked Storage Capacitor on Flotox Cell for Megabit NVRAM Applications", from 1989 International Electron Devices Meeting Technical Digest, pages IEDM 89-595 through 598. These references are incorporated herein by reference.
A design related to that of the present invention is described in the article submitted herewith as Appendix A, entitled "A 256-bit Non-Volatile Dynamic RAM With ECC and Redundancy", by Fukumoto et al., which is incorporated herein by reference.
An NVDRAM memory device, as has been described by Dimaria in U.S. Pat. No. 4,471,471, comprises an array of NVDRAM cells. Each NVDRAM cell includes a DRAM cell and an EEPROM cell. The DRAM cell, which typically includes a MOS transistor in series with a storage capacitor, is volatile, while the EEPROM cell, which stores data in the form of charge on a floating gate in a floating gate MOS transistor, is non-volatile. The advantage of the NVDRAM is that while data may be quickly read from and written to the DRAM during normal operation, it can be stored in the non-volatile EEPROM during power down. The EEPROM data in an NVDRAM, however, is not directly accessible and must be transferred to the DRAM before being read.
An NVDRAM has at least three operating modes: (1) a DRAM read/write mode in which the NVDRAM operates like a regular DRAM; (2) a store mode in which the DRAM data is transferred to the EEPROM to be stored; and (3) a recall mode in which the EEPROM data is transferred to the DRAM to be accessed.
In the normal DRAM read/write operating mode, the EEPROM transistor is turned off, and data are written to and read from the DRAM cell in the conventional manner --namely, the DRAM transistor is turned on when data is to be stored on or read from the DRAM storage capacitor and, otherwise, is turned off.
When the DRAM data needs to be stored in the EEPROM, a store operation, which transfers the DRAM data to the EEPROM, is executed. The data is now stored as charge on the floating gate of the EEPROM transistor. When the EEPROM data needs to be recalled to the DRAM, a recall operation is executed. This operation involves sensing the logic state of the EEPROM and, accordingly, charging a full logic state 1 or logic state 0 voltage level onto the DRAM storage capacitor.
In static-RAM-based NVRAM devices in current use, each memory cell is essentially a cross-coupled latch which has two stable operating states. These stable states are established by active circuit elements within each of the memory cells. The active circuit elements act either as a pull-up, providing a full rail logic 1 state, or as a pull-down, providing a full rail logic 0 state. Since each memory cell has the same pullup or pull-down capability, each can independently achieve the full rail logic states. Either a capacitive or current imbalance is established in each memory cell by the programmed state of the EEPROM portion of each cell.
During the recall operation in such an NVDRAM, both sides of the latch are initially set to the same potential, and they are then allowed to charge from that point. The imbalance between the two sides of the cell causes the two sides to charge at different rates, such that the latch will be predisposed to one of the two stable states. Therefore, once the latch is set, these two states will be full rail logic 0 or logic 1 voltage levels. Because of this design of static-RAM-based NVRAM devices, no external initiation of the restore function is necessary to place full logic levels in the memory cells. In addition, such NVRAM devices are able to use a block mode recall operation, in which all data in all memory cells in the device are transferred from EEPROM to RAM simultaneously.
In contrast, in a dynamic-RAM-based NVRAM device (NVDRAM), the memory cells have no built-in restore capability. Unlike in a static-RAM-based NVRAM, data in each memory cell of an NVDRAM is stored as a variable charge on a capacitor. There are no active pull-up or pull-down circuit elements within each cell. Consequently, there is no means for altering the capacitor charge on each cell independently. Therefore, circuitry external to the memory cell itself must be used to provide a full rail logic 0 or logic 1 potential on the memory cell capacitor.
Lacking an externally initiated restore operation following an EEPROM to DRAM data recall in an NVDRAM device, the memory cells will contain degraded logic state 0 or 1 voltage levels. When the data in the DRAM memory cells are subsequently read out conventional DRAM fashion, these degraded memory cell states may result in incorrect data being sensed. Therefore, it is necessary to perform a conventional DRAM restore operation during the recall operation to ensure full logic state 0 or 1 voltage levels in the DRAM cell. This restore operation can only reliably occur to one memory cell per bit line at any one time. Thus, in a DRAM-based NVRAM device (NVDRAM), simultaneous recall of all memory cells (i.e. block mode recall) is not feasible; only one memory cell per bit line should be recalled at any one time.